1. Field of the Invention
The present invention relates to a semiconductor device having a self-testing function and a method for testing the semiconductor device, and more particularly, to a semiconductor device having a function to test a plurality of macro blocks and a method for testing the macro blocks.
2. Description of the Related Art
FIG. 7 is a block diagram for explaining a semiconductor device having a self-testing function and a method for testing the semiconductor device.
In the semiconductor device shown in FIG. 7, in a normal operation mode, input data Din is supplied to each of macro blocks 751, 752. and 75m, . . . Each of macro blocks 751, 752, . . . and 75m process the input data Din and output the processed data Dout.
In a test mode, test circuit 71 supplies test data (data used for testing) TTD to a circuit block 74 via a test bus 72. The test data TTD is input to m (m represents an integer more than 1) macro blocks 751, 752, . . . and 75m in the circuit block 74. Bus selectors 791, 792, . . . and 79m respectively included in the macro blocks 751, 752, . . . and 75m supply the test data TTD from the test circuit 71 to network circuits 761, 762, . . . and 76m. Each of the network circuits 761, 762, . . . and 76m process the test data TRD and output processed data TRD to the test circuit 71 through test buses 731, 732, . . . and 73m, respectively. The test circuit 71 compares the supplied processed data TRD with the expected value.
In the semiconductor device shown in FIG. 7, the test data TTD output from the test circuit 71 is supplied parallel to all of the macro blocks 751, 752, . . . and 75m, and processed parallel by the macro blocks 751, 752, . . . and 75m. Further, the respective processed data TRD of the macro blocks 751, 752, . . . and 75m are transmitted parallel to the test circuit 71. Due to this parallelism, regardless of the number of the macro blocks 751, 752, . . . and 75m, time period required for the test is almost the same as time period for testing a single macro block.
FIG. 8 is a block diagram for explaining another example of a conventional semiconductor device having a self-testing function. In the semiconductor device shown in FIG. 8, a test circuit 81 supplies test data TTD to a circuit block 84 via a test bus 82. A bus selector 89i (i represents an integer from 1 to m) selected by the test circuit 81 from among m bus selectors 891, 892, . . . and 89m respectively included in macro blocks 851, 852, . . . and 85m supplies the test data TTD to a network circuit 86i in the selected macro block 85i. The network circuit 86i processes the test data TTD and outputs processed data TRD. A bus selector 88i supplies the processed data TRD to the test circuit 81 via a test bus 83. The test circuit 81 compares the received processed data TRD with the expected value.
The test circuit 81 repeats the above stated testing procedures for all the macro blocks, selecting one macro block at a time. FIGS. 9A and 9B are time charts showing the testing procedures of the semiconductor device shown in FIG. 8. As known from FIGS. 9A and 9B, time period for testing the semiconductor device shown in FIG. 8 is calculated by the equation below.
time period for testing the semiconductor device=(transmission time of the test data)xc3x97(number of macro blocks)+(time period for changing macro blocks)xc3x97(number of macro blocksxe2x88x921)+delay time
The delay is caused by internal transmission of data in a macro block, most part of which is a time period required for data processing by a macro block.
The semiconductor device shown in FIG. 7 requires the same number of test buses and circuits for comparing the processed data TRD with the expected data, as the number of macro blocks. Therefore, this semiconductor device requires a large occupation area.
The semiconductor device shown in FIG. 8 cannot test a plurality of macro blocks parallel or at a time. Thus, if the number of macro blocks to be tested increases, more time is needed for testing those macro blocks.
An example of a semiconductor device which performs testing by individually transmitting test data to a plurality of macro blocks as shown in FIG. 8 is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H2-10179. In testing, the semiconductor device disclosed in this publication selects a macro block to be tested under control by a test interface circuit equipped in each macro block, transmits test data to the selected macro block and tests this macro block individually. This disclosure is incorporated herein by reference.
Accordingly, it is an object of the present invention to provide a semiconductor device having a testing function and a method for testing a plurality of macro blocks in a short period of time.
It is another object of the present invention to provide a semiconductor device with a self-testing function which occupies a small area.
To achieve the above objects, a semiconductor device with a self-testing function according to the first aspect of the present invention comprises:
a first to n-th (n is an integer more than 1) macro blocks each of which receives input data, processes the input data, and outputs processed data;
a data path which supplies data to-be-processed to the n macro blocks, and transmits processed data processed by and output from the n macro blocks respectively, in a normal operation mode;
a test circuit which outputs test data for testing the n macro blocks and receives the test data processed by the n macro blocks, in a test mode; and
a test path which supplies the test data output from the test circuit to the first macro block, supplies data output from the h-th (h is an integer from 1 to (nxe2x88x921)) macro block to the (h+1)th macro block and supplies data output from the n-th macro block to the test circuit.
The test path may comprise: a first test bus which transmits the test data output from the test circuit to the first macro block; connectors which transmit data output from the h-th macro block to the (h+1)th macro block; and a second test bus which transmits data output from the n-th macro block to the test circuit.
The test circuit may compare data received from the n-th macro block and an expected value, and detects that there is defect if received data substantially does not coincide with the expected value.
The test circuit may comprises: a supplier which supplies the test data; and a comparator which compares expected data with data received from the n-th macro block.
The test circuit may further comprise: a controller which designates j-th (j is an integer from 1 to n) macro block. In this case, it is desirable that the supplier supplies test data for testing the j-th macro block designated by the controller, the comparator compares expected data for the j-th macro block with data output from the j-th macro block, and the test path transmits the test data for testing the j-th macro block supplied from the supplier to the j-th macro block and supplies data output from the j-th macro block to the comparator.
For example, the controller performs control to test the j-th macro block individually, if any defect is found by the test circuit.
The test circuit may comprise a controller which designates j-th (j is an integer from 1 to n) macro block, a supplier which supplies test data for testing the j-th macro block designated by the controller, and a comparator which compares expected data for j-th macro block with data output from the j-th macro block. And the test path may further transmit the test data for testing the j-th macro block supplied from the supplier to the j-th macro block and supply data output from the j-th macro block to the comparator.
The semiconductor device may further comprise a second test path which supplies the test data to one of the macro blocks designated by the test circuit and transmits data which is the test data processed by the designated macro block. In this case, it is desirable that the test circuit tests all of the macro blocks with the test path, and if any defect is found in the macro blocks, then, tests each of the n macro blocks with the second test path, sequentially.
For example, the data path comprises a selector, first to n-th input terminal connectors and first to n-th output terminal connectors, and the first to n-th macro blocks include first to n-th circuits, respectively. In this case, for example, the selector selects one from between the test data supplied from the test circuit and the to-be-processed data of the first circuit and supplies selected one to the first input terminal connector, the first input terminal connector supplies an output from the selector to an input terminal of the first circuit; the k-th input terminal connector selects one from between an externally supplied to-be-processed data of the k-th circuit and an output from the kxe2x88x921)th output terminal connector and supplies selected one to an input terminal of the k-th circuit; the n-th input terminal connector selects one from between an externally supplied to-be-processed data of n-th circuit and an output from the (nxe2x88x921)th output terminal connector and supplies selected one to an input terminal of the n-th circuit; the first output terminal connector externally outputs an output from an output terminal of the first circuit or supplies the output from the output terminal to the second input terminal connector; the k-th output terminal connector externally outputs an output from an output terminal of the k-th circuit or supplies the output from the output terminal to the (k+1)th input terminal connector; and the n-th output terminal connector externally outputs an output from an output terminal of the n-th circuit or supplies the output from the output terminal to the test circuit. In a normal operation mode: the selector selects the to-be-processed data of the first circuit and supplies the to-be-processed data to the first input terminal connector, m-th (m is an integer from 2 to n) input terminal connector selects the to-be-processed data from the selector and supplies the to-be-processed data to the input terminal of the m-th circuit; and the m-th output terminal connector selects and externally outputs an output from an output terminal of the m-th circuit. On the other hand, in a test mode, the selector selects the test data output from the test circuit and supplies the test data to the first input terminal connector, the first input terminal connector supplies an output from the selector to the input terminal of the first circuit; the k-th input terminal connector selects an output from the (kxe2x88x921)th output terminal connector and supplies selected output to the input terminal of the k-th circuit; the n-th input terminal connector selects an output from the (nxe2x88x921)th output terminal connector and supplies selected output to the input terminal of the n-th circuit; the first output terminal connector supplies an output from the output terminal of the first circuit to the second input terminal connector, the k-th output terminal connector supplies an output from the output terminal of the k-th circuit to the (k+1)th input terminal connector, and the n-th output terminal connector supplies an output from the output terminal of the n-th circuit to the test circuit.
For example, each of the selector and the second to n-th input terminal connectors comprises a multiplexer of two inputs 1 one output type, and each of the output terminal connectors comprises a switch of one inputs/two outputs type.
The data path and the test path may comprise first to n-th selectors, first to n-th input terminal connectors and first to n-th output terminal connectors. In this case, the first to n-th macro blocks include first to n-th circuits, respectively; the first selector selects one from between an output from the second selector and to-be-processed data of the first circuit and supplies selected one to the first input terminal connector, the k-th k is a natural number from 2 to (nxe2x88x921)) selector selects one from between an output from the (k+1)th selector and the to-be-processed data of the k-th circuit and supplies selected one to the k-th input terminal connector or the (kxe2x88x921)th selector; the n-th selector selects one from between the test data supplied from the test circuit and the to-be-processed data of the n-th circuit and supplies selected one to the n-th input terminal connector or the (nxe2x88x921)th selector, the first input terminal connector supplies an output from the first selector to an input terminal of the first circuit; the k-th input terminal connector selects one from between an output from the k-th selector and an output from the (kxe2x88x921)th output terminal connector and supplies selected one to an input terminal of the k-th circuit or the k-th output terminal connector, the n-th input terminal connector selects one from between an output from the n-th selector and an output from the (nxe2x88x921)th output terminal connector and supplies selected one to an input terminal of the n-th circuit or the n-th output terminal connector; the first output terminal connector externally outputs an output from an output terminal of the first circuit or supplies the output from the output terminal to the second input terminal connector; the k-th output terminal connector selects one from between an output from an output terminal of the k-th circuit and an output from the k-th input terminal connector and externally outputs selected one or supplies the selected one to the (k+1)th input terminal connector; and the n-th output terminal connector selects one from between an output from an output terminal of the n-th circuit and an output from the n-th input terminal connector and externally outputs selected one or supplies the selected one to the test circuit. In a normal operation mode, the m-th (m is a natural number from 1 to n) selector selects the to-be-processed data of the m-th circuit and supplies the to-be-processed data to the m-th input terminal connector, the m-th input terminal connector selects the to-be-processed data from the m-th selector and supplies the to-be-processed data to an input terminal of the m-th circuit; and the m-th output terminal connector selects and externally outputs an output from an output terminal of the m-th circuit. In a first test mode, the n-th selector selects the test data output from the test circuit and supplies the test data to the (nxe2x88x921)th selector; the k-th selector selects an output from the (k+1)th selector and supplies selected output to the (kxe2x88x921)th selector, the first selector selects an output from the second selector and supplies selected output to the first input terminal connector; the first input terminal connector supplies the output from the first selector to the input terminal of the first circuit; the k-th input terminal connector selects an output from the (kxe2x88x921)th output terminal connector and supplies selected output to the input terminal of the k-th circuit; the n-th input terminal connector selects an output from the (nxe2x88x921)th output terminal connector and supplies selected output to the input terminal of the n-th circuit; the first output terminal connector selects an output from the output terminal of the first circuit and supplies the output to the second input terminal connector, the k-th output terminal connector selects an output from the output terminal of the k-th circuit and supplies selected output to the (k+1)th input terminal connector, and the n-th output terminal connector selects an output from the output terminal of the n-th circuit and supplies selected output to the test circuit. In a second test mode where the controller designates the j-th circuit, the j-th selector selects the test data supplied from the test circuit and supplies the test data to the j-th input terminal connector; the j-th input terminal connector selects an output from the j-th selector and supplies selected output to an mput terminal of the j-th circuit; and the j-th output terminal connector selects an output from an output terminal of the j-th circuit and supplies the output to the test circuit.
For example, the first selector comprises a switch of two inputs/one output type, the k-th selector comprises a switch of two inputs/two outputs type and the n-th selector comprises a switch of two inputs/two outputs type; the k-th input terminal connector comprises a switch of two inputs/two outputs type and the n-th input terminal connector comprises a switch of two inputs/two outputs type; and the first output terminal connector comprises a switch of two inputs/two outputs type, the k-th output terminal connector comprises a switch of two inputs/two outputs type and the n-th output terminal connector comprises two inputs/two outputs type.
To achieve the above objects, a method for testing a semiconductor device which comprises first to n-th (n is a natural number more than 1) macro blocks, according to the second aspect of the present invention comprises:
a method for testing a semiconductor device which comprises first to n-th (n is a natural number more than 1) macro blocks, the method comprising:
supplying test data for testing the n macro blocks to the first macro block;
processing in the first macro block, the test data and outputting processed test data;
supplying data output from the h-th (h is a natural number from 1 to (nxe2x88x921)) macro block to the (h+1)th macro block;
processing in the (h+1)th macro block, the data supplied to the (h+1)th macro block and outputting the processed data from the (h+1)th macro block;
supplying data output from the n-th macro block to the test circuit; and
comparing, in the test circuit, the data output from the n-th macro block with expected data.